MT46V2M32V1 Description
4U t DOUBLE eDATA RATE e h (DDR) S SDRAM a t a D.
MT46V2M32V1 Key Features
- 512K x 32 x 4 banks
- Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture
- Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
- Reduced output drive option
- Differential clock inputs (CK and CK#)
- mands entered on each positive CK edge
- DQS edge-aligned with data for READs; centeraligned with data for WRITEs
- DLL to align DQ and DQS transitions with CK
- Four internal banks for concurrent operation
- Data mask (DM) for masking write data