MT46V64M8
Key Features
- Bidirectional data strobe (DQS) transmitted/
- Internal, pipelined double-data-rate (DDR)
- Differential clock inputs (CK and CK#)
- mands entered on each positive CK edge
- DQS edge-aligned with data for READs; center
- DLL to align DQ and DQS transitions with CK
- Four internal banks for concurrent operation
- Data mask (DM) for masking write data
- Auto refresh
- Longer-lead TSOP for improved reliability (OCPL)
