MT48H4M32LF
Key Features
- Mobile Low-Power SDR SDRAM
- VDD/VDDQ = 1.7–1.95V
- Fully synchronous; all signals registered on positive edge of system clock
- Internal, pipelined operation; column address can be changed every clock cycle
- 4 internal banks for concurrent operation
- Programmable burst lengths (BL): 1, 2, 4, 8, and continuous
- Auto precharge, includes concurrent auto precharge
- Auto refresh and self refresh modes
- On-chip temperature sensor to control self refresh rate
- Partial-array self refresh (PASR)
