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MT48LC4M32B2 - SDR SDRAM

Features

  • Features.
  • PC100-compliant.
  • Fully synchronous; all signals registered on positive edge of system clock.
  • Internal pipelined operation; column address can be changed every clock cycle.
  • Internal banks for hiding row access/precharge.
  • Programmable burst lengths: 1, 2, 4, 8, or full page.
  • Auto precharge, includes concurrent auto precharge and auto refresh modes.
  • Self refresh mode (not available on AT devices).
  • Auto refresh.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SDR SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks 128Mb: x32 SDRAM Features Features • PC100-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge and auto refresh modes • Self refresh mode (not available on AT devices) • Auto refresh – 64ms, 4096-cycle refresh (commercial and industrial) – 16ms, 4096-cycle refresh (automotive) • LVTTL-compatible inputs and outputs • Single 3.3V ±0.
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