MT48LC4M32B2 Overview
SDR SDRAM MT48LC4M32B2 1 Meg x 32 x 4 Banks 128Mb:.
MT48LC4M32B2 Key Features
- PC100-pliant
- Fully synchronous; all signals registered on positive
- Internal pipelined operation; column address can
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto precharge, includes concurrent auto precharge
- Self refresh mode (not available on AT devices)
- Auto refresh
- 64ms, 4096-cycle refresh (mercial and industrial)
- 16ms, 4096-cycle refresh (automotive)