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MT48LC8M32B2 - SYNCHRONOUS DRAM

Description

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits.

It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Features

  • PC100 functionality.
  • Fully synchronous; all signals registered on positive edge of system clock.
  • Internal pipelined operation; column address can www. DataSheet4U. com be changed every clock cycle.
  • Internal banks for hiding row access/precharge.
  • Programmable burst lengths: 1, 2, 4, 8, or full page.
  • Auto Precharge, includes.

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Full PDF Text Transcription

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PRELIMINARY 256Mb: x32 SDRAM SYNCHRONOUS DRAM FEATURES • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can www.DataSheet4U.com be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh (15.6µs/row) • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply • Supports CAS latency of 1, 2, and 3 MT48LC8M32B2 - 2 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.
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