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MT4C16270 - DRAM 256K X 16 DRAM 5V / EDO PAGE MODE

General Description

The MT4C16270 is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x16 configuration.

The MT4C16270 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins.

Key Features

  • Industry-standard x16 pinouts, timing, functions and packages.
  • High-performance CMOS silicon-gate process.
  • Single +5V ±10% power supply.
  • Low power, 3mW standby; 300mW active, typical.
  • All device pins are TTL-compatible.
  • 512-cycle refresh in 8ms (9 row- and 9 column addresses).
  • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN.
  • Extended Data-Out (EDO) PAGE MODE access cycle.
  • BYTE WRITE and BYTE READ a.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TECHNOLOGY, INC. MT4C16270 256K x 16 DRAM DRAM FEATURES • Industry-standard x16 pinouts, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply* • Low power, 3mW standby; 300mW active, typical • All device pins are TTL-compatible • 512-cycle refresh in 8ms (9 row- and 9 column addresses) • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • Extended Data-Out (EDO) PAGE MODE access cycle • BYTE WRITE and BYTE READ access cycles 256K x 16 DRAM 5V, EDO PAGE MODE PIN ASSIGNMENT (Top View) 40-Pin SOJ (DA-6) OPTIONS • Timing 40ns access 50ns access 60ns access • Packages Plastic SOJ (400 mil) MARKING -4* -5* -6 DJ • Part Number Example: MT4C16270DJ-4 *40ns and 50ns access specifications are limited to a VCC range of ±5%.