Datasheet4U Logo Datasheet4U.com

MT4C1M16E5 - EDO DRAM

Download the MT4C1M16E5 datasheet PDF. This datasheet also covers the MT4LC1M16E5 variant, as both devices belong to the same edo dram family and are provided as variant models within a single manufacturer datasheet.

Description

The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration.

The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#).

Features

  • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages.
  • High-performance CMOS silicon-gate process.
  • Single power supply (+3.3V ±0.3V or 5V ±10%).
  • All inputs, outputs and clocks are TTL-compatible.
  • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S).
  • BYTE WRITE access cycles.
  • 1,024-cycle refresh (10 row, 10 column addresses).
  • Extended Data-Out (EDO) PAGE MODE access.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT4LC1M16E5_MicronTechnology.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MT4C1M16C3 1 MEG x 16 FPM DRAM Micron
MT4C1004J883C 4 MEG x 1 DRAM FAST PAGE MODE Austin Semiconductor
MT4C4001J 1 MEG x 4 DRAM Micross
MT4C4001J 1 MEG x 4 DRAM Fast Page Mode DRAM Austin Semiconductor
MT4C4256 256K x 4 DRAM Austin Semiconductor

Other Datasheets by Micron Technology

Part Number Description
MT4C1024 1M x 1 DRAM
MT4C1024-883C 1M x 1 DRAM
MT4C1024E (MT4C1024E / MT4C4256E) 1 MEG PAGE MODE DRAM
MT4C1024L 1M x 1 DRAM
MT4C1025 1M x 1 DRAM

Full PDF Text Transcription

Click to expand full text
16Mb: 1 MEG x16 EDO DRAM EDO DRAM MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or 5V ±10%) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S) • BYTE WRITE access cycles • 1,024-cycle refresh (10 row, 10 column addresses) • Extended Data-Out (EDO) PAGE MODE access • 5V-tolerant inputs and I/Os on 3.
Published: |