MT4LC4M4B1 Overview
The 4 Meg x 4 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits.
MT4LC4M4B1 Key Features
- Industry-standard x4 pinout, timing, functions, and packages
- High-performance, low-power CMOS silicon-gate process
- Single power supply (+3.3V ±0.3V or +5V ±0.5V)
- All inputs, outputs and clocks are TTL-patible
- Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR)
- Optional self refresh (S) for low-power data retention
- 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)
- FAST-PAGE-MODE (FPM) access
- 5V tolerant inputs and I/Os on 3.3V devices
- Voltage 3.3V 5V