MT9LSDT872 Overview
ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SYNCHRONOUS DRAM MODULE.
MT9LSDT872 Key Features
- JEDEC-standard 168-pin, dual in-line memory module (DIMM)
- PC133- and PC100-pliant
- Registered inputs with one-clock delay
- Phase-lock loop (PLL) clock driver to reduce loading
- Utilizes 133 MHz and 125 MHz SDRAM ponents
- ECC-optimized pinout
- 64MB (8 Meg x 72) and 128MB (16 Meg x 72)
- Single +3.3V ±0.3V power supply
- Fully synchronous; all signals registered on positive edge of PLL clock
- Internal pipelined operation; column address can be changed every clock cycle