MT4LC1M16C3 Overview
The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
MT4LC1M16C3 Key Features
- JEDEC- and industry-standard x16 timing, functions, pinouts, and packages
- High-performance, low-power CMOS silicon-gate process
- Single power supply (+3.3V ±0.3V or 5V ±0.5V)
- All inputs, outputs and clocks are TTL-patible
- Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN
- Optional self refresh (S) for low-power data retention
- BYTE WRITE and BYTE READ access cycles
- 1,024-cycle refresh (10 row, 10 column addresses)
- FAST-PAGE-MODE (FPM) access
- Voltage 1 3.3V 5V