SM512M64Z01MD4BNK-053FT Datasheet | Micron Technology

Features Mobile LPDDR4 SDRAM SM256M64Z01MD4BNK-053FT, SM512M64Z01MD4BNK-053FT Features - Ultra-low-voltage core and I/O power supplies - VDD1 = 1.70- 1.95V; 1.8V nominal - VDD2/VDDQ = 1.06- 1.17V; 1.10V nominal - Frequency range - 1866- 10 MHz (data rate range: 3733- 20 Mb/s/ pin) - 16n prefetch DDR architecture - 2-channel partitioned architecture for low RD/WR energy and low average latency - 8 internal banks per channel for concurrent opera- tion - Single-data-rate CMD/ADR entry - Bidirectional/differential data strobe per byte lane - Programmable READ and WRITE latencies (RL/WL) - Programmable and on-the-fly burst lengths (BL = 16, 32) - Directed per-bank refresh for concurrent bank op- eration and ease of mand scheduling - Up to 14.9 GB/s per die (2 channels x 7.4 GB/s) - On-chip temperature sensor to control self refresh rate - Partial-array self refresh (PASR) - Selectable output drive strength (DS) - Clock-stop capability - Ro HS-pliant, “green” packaging - Programmable VSSQ (ODT) termination Options - VDD1/VDD2: 1.8V/1.1V - Array configuration - 256 Meg x 64 (4 channels x16 I/O) - 512 Meg x 64 (4 channels x16 I/O) - Device configuration - 2 x 256M32 die in package - 4 x 256M32 die in package - FBGA “green” package - 366-ball WFBGA (15mm x 15mm) - Speed grade, cycle time - 535ps @ RL = 32/36 - 625ps @ RL = 28/32 - Operating temperature range - - 30°C to...