VSP9442A Datasheet | Micronas Semiconductor

Features Block Diagram Functional Description CVBS Frontend Source Select Signal Levels and Gain Control Clamping Synchronization Chroma Decoder Luminance Processing RGB Front-end Source Select Signal Magnitudes and Gain Control Clamping Digital Prefiltering RGB → YUV Matrix Contrast, Brightness and Saturation Control of Input Signal Soft Mix Static Switch mode Static Mixer mode Dynamic Mixer mode FBL Activity and Overflow Detection Input Processing Horizontal Prescaler Noise Reduction Noise Measurement Letterbox Detection Output Processing Horizontal Postscaler Panorama Mode Operation Modes Display Processing Peaking Digital Color Transition Improvement (DCTI) Coarse and Fine Delay Oversampling and DAC Output-Sync Controller HOUT Generator VOUT Generator BLANK Generator Background Generator Window Function Digital 656 Input Digital 656 Output Clock Concept PRELIMINARY DATA SHEET Aug. 28, 2002; 6251-552-4PD Micronas Data Sheet 4 U . .. PRELIMINARY DATA SHEET VSP 94x2A Contents, continued Page 32 34 34 34 40 46 52 105 105 105 109 110 112 114 114 115 116 116 119 120 122 124 Section 2.6.1. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.3.1. 4.6.3.2. 5. 5.1. 6. Title Linelocked Clock Generator I2C Bus Interface I2C Bus Slave Address I2C Bus Format I2C Bus List in Alphabetical Order I2C Bus mand Table I2C Bus mand Description Specifications Outline Dimensions Pin Connections and Short Descriptions for VSP 9402/32 and VSP 9412/421) Differing Pin Connections and Short Descriptions for VSP 9412/42 Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Remended Operating Conditions Characteristics General Characteristics I2C Bus Characteristics Application Circuit Application Overview Data Sheet History Micronas Aug. 28, 2002; 6251-552-4PD Data Sheet 4 U . .. VSP 94x2A Powerful Scan-Rate Converter including Multistandard Color Decoder Release Note: Revision bars indicate significant...