DPL4519G Datasheet | Micronas

Features of the DPL 4519G Application Fields of the DPL 4519G Functional Description Architecture of the DPL 4519G Family Preprocessing I2S Input Signals Selection of Internal Processed Surround Signals Source Selection and Output Channel Matrix Audio Baseband Processing Main and Aux Outputs Surround Processing Surround Processing Mode Decoder Matrix Surround Reproduction Center Modes Useful binations of Surround Processing Modes Examples Application Tips for using 3D-PANORAMA Sweet Spot Clipping Loudspeaker Requirements Cabinet Requirements Input and Output Levels for Dolby Surround Pro Logic SCART Signal Routing SCART Out Select Stand-by Mode I2S Bus Interfaces Synchronous I2S-Interface(s) Asynchronous I2S-Interface Multichannel I2S-Output Asynchronous Multichannel I2S-Input Digital Control I/O Pins Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Device and Subaddresses Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General DPL 4519G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C Controlling PRELIMINARY DATA SHEET 7 7 8 8 8 8 8 8 8 8 9 9 9 10 11 11 11 11 11 11 11 11 12 12 12 12 12 12 13 13 14 14 14 14 15 15 16 16 16 16 16 16 Micronas PRELIMINARY .. DATA SHEET DPL 4519G Contents, continued Page 16 16 19 19 21 21 33 34 34 34 35 35 37 40 43 45 47 47 48 48 48 49 50 50 51 52 53 54 56 58 58 61 61 62 64 Section 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.4. 3.5. 3.5.1. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 5. 5.1. 5.2. 6. Title DPL 4519G Programming Interface User Registers Overview Description of User Registers Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of...