DRX3960A Datasheet | Micronas

Features Quick Reference Data Analog TV Application Initialization for Analog TV Multistandard Configuration for B/G, L, I, D/K and M/N Multistandard Configuration for L’ FM Radio Functional Description Input Amplifier with TOP Setting Carrier Recovery Channel Filtering and Audio/Video Splitting Video and Tuner AGC Group Delay Equalizing Peaking SIF AGC Output Ports Standard Specific Filter Curves Standard B Standard G Standard D/K, I, L/L’ Standard M/N Standard FM ADVANCE INFORMATION .. Control Interface I2C Bus Interface Device and Subaddresses Description of CONTROL Register Protocol Description Proposals for General DRX 3960A I2C Telegrams Symbols Write Telegrams Read Telegrams List of Control Registers List of Status Registers Description of User Registers Write Register on I2C Subaddress 03hex Write Register on I2C Subaddress 10hex Read Register on I2C Subaddress 11hex Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Electrical Characteristics Micronas . 4U. .Data Sheet 4U. .. ADVANCE INFORMATION DRX 3960A Contents, continued Page 23 23 24 24 24 28 30 Section 5.5.1. 5.5.2. 5.5.3. 5.5.4. 5.6. 6. 7. Title Absolute Maximum Ratings Remended Operating Conditions Remended Crystal Characteristics Remended Tuner Characteristics Characteristics Application Circuit Data Sheet History .. Micronas 3 . 4U. .Data Sheet 4U. .. DRX 3960A Digital Receiver Front-end Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The Digital Receiver Front-end DRX 3960A performs the entire multistandard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation, and generation of the second sound IF (SIF) with only one SAW filter. The IC is designed for applications in TV sets, VCRs, PC cards, and TV tuners. The alignment-free DRX 3960A needs no special external ponents. All control functions and status registers are accessible via I2C bus interface. Therefore, it...