MSP3410G Datasheet | Micronas

Features of the MSP 34x0G Family MSP 34x0G Version List MSP 34x0G Versions and their Application Fields Functional Description Architecture of the MSP 34x0G Family Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Manual Mode Preprocessing for SCART and I2S Input Signals Source Selection and Output Channel Matrix Audio Baseband Processing SRS WOW BBE High Definition Sound Micronas VOICE Automatic Volume Correction (AVC) Loudspeaker and Headphone Outputs Subwoofer Output Quasi-Peak Detector Micronas BASS (MB) Dynamic Amplification Adding Harmonics Micronas BASS Parameters SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode I2S Bus Interface ADR Bus Interface Digital Control I/O Pins and Status Change Indication Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General MSP 34x0G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling MSP 34x0G Programming Interface 2 May 27, 2003; 6251-476-1DS DATA SHEET Micronas DATA SHEET Contents, continued Page Section Title 3.3.1. User Registers Overview 3.3.2. Description of User Registers 24 3.3.2.1. STANDARD SELECT Register 24 3.3.2.2. Refresh of STANDARD SELECT Register 24 3.3.2.3. STANDARD RESULT Register 3.3.2.4. Write Registers on I2C Subaddress 10hex 3.3.2.5. Read Registers on I2C Subaddress 11hex 3.3.2.6. Write Registers on I2C Subaddress 12hex 3.3.2.7. Read Registers on I2C Subaddress 13hex 43 3.4. Programming Tips 43 3.5. Examples of Minimum Initialization Codes 3.5.1. B/G-FM (A2 or...