A3P125 Overview
Revision 13 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support.
A3P125 Key Features
- 15 k to 1 M System Gates
- Up to 144 kbits of True Dual-Port SRAM
- Up to 300 User I/Os
- 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
- Instant On Level 0 Support
- Single-Chip Solution
- Retains Programmed Design when Powered Off
- 350 MHz System Performance
- 3.3 V, 66 MHz 64-Bit PCI†
- ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG
