ZL30182 Overview
Register Map: Section.
ZL30182 Key Features
- Two Independent Channels
- Three Input Clocks Per Channel
- Three inputs, two differential/CMOS, one CMOS
- Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS)
- Inputs continually monitored for activity and frequency accuracy
- Automatic or manual reference switching
- Low-Bandwidth DPLL Per Channel
- Programmable bandwidth, 5Hz to 500Hz
- Attenuates jitter up to several UI
- Freerun or holdover on loss of all inputs