ZL30255 Datasheet | Microsemi

Register Map: Section 6.2 Features - Two Independent Channels - Three Input Clocks Per Channel - Three inputs, two differential/CMOS, one CMOS - Any input frequency from 1k Hz to 1250MHz (1k Hz to 300MHz for CMOS) - Inputs continually monitored for activity and frequency accuracy - Automatic or manual reference switching - Low-Bandwidth DPLL Per Channel - Programmable bandwidth, 14Hz to 500Hz - Attenuates jitter up to several UI - Freerun or digital hold on loss of all inputs - Digitally controlled phase adjustment - Low-Jitter Fractional-N APLL and 3 Outputs Per Channel - Any output frequency from <1Hz to 1035MHz - High-resolution fractional frequency conversion with 0ppm error - Easy-to-configure, encapsulated design requires no external VCXO or loop filter ponents - Each output has independent dividers - Output jitter is typically 0.16 to 0.28ps RMS (12k Hz-20MHz integration band) - Outputs are CML or 2x CMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL Each Channel: IC1P, IC1N IC2P, IC2N IC3P/GPIO3 HSDIV1 HSDIV2 HSDIV3 Input Block Divider, Monitor, Selector Figure 9 XA xtal XB driver ×2 DPLL Jitter Filtering, Digital...