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ZL30773 - IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers

Download the ZL30773 datasheet PDF. This datasheet also covers the ZL30771 variant, as both devices belong to the same ieee 1588 & synchronous ethernet packet clock network synchronizers family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • One, Two or Three DPLL Channels.
  • Packet and/or physical-layer frequency, phase and time synchronization.
  • Physical-layer compliance with ITU-T G.8262, G.8261.1, G.813, G.812, Telcordia GR-1244, GR-253.
  • Packet-timing compliance with ITU-T G.8261, G.8263, G.8273.2 (class A, B, C, D), G.8273.4.
  • Enables 5G wireless.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ZL30771-Microsemi.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
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ZL30734 PTP & SyncE Network Synchronizers Microchip
ZL30735 PTP & SyncE Network Synchronizers Microchip

Other Datasheets by Microsemi (now Microchip Technology)

Part Number Description
ZL30771 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers
ZL30772 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers
ZL30791 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers
ZL30793 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers
ZL30795 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Features • One, Two or Three DPLL Channels • Packet and/or physical-layer frequency, phase and time synchronization • Physical-layer compliance with ITU-T G.8262, G.8261.1, G.813, G.812, Telcordia GR-1244, GR-253 • Packet-timing compliance with ITU-T G.8261, G.8263, G.8273.2 (class A, B, C, D), G.8273.4 • Enables 5G wireless applications with sub100ns time/phase alignment requirements • Programmable bandwidth, 0.1mHz to 470Hz • Hitless reference switching and mode switching • High-resolution holdover averaging • Programmable phase slope limit for transients, downto 1 ns/s • Per-DPLL phase adjustment, 1ps resolution • Input Clocks • Accepts up to 10 differential or CMOS inputs • Any input frequency from 0.