AS4DDR264M72PBG1 Datasheet | Micross

i PEM 4.8 Gb SDRAM-DDR2 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS i NTEGRATED Plastic Encapsulated Microcircuit Features DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: - Proprietary Enchanced Die Stacked i PEM - 208 Plastic Ball Grid Array (PBGA), 16 x 23mm - 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data - output drive strength 1.8V ±0.1V mon core power and I/O supply Programmable CAS latency: 3, 4, 5, 6 or 7 Posted CAS additive latency: 0, 1, 2, 3, 4 or 5 Write latency = Read latency - 1- t CK Organized as 64M x 72 Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical BENEFITS...