Description
3 MXT3010 features 4 MXT3010 subsystems 5 What information is in this manual 6 CHAPTER 2 The SWAN Processor The SWAN advantage 10 9 SWAN’s instructions and address spaces 10 MXT3010 Reference Manual iii Instruction execution 13 Instruction space organization Instruction cache 15 14 SWAN processor instruction classes 18 Arithmetic Logic Unit (ALU) instructions 19 Branch instructions 19 Registers 21 24 Flag registers HEC generation and check circuit 25 CHAPTER 3 The Cell Scheduling System 27 How the Cell Scheduling System works 28 Data transmission - servicing and scheduling 31 Servicing 31 Scheduling 32 Pacing the transmission rate of cells 37 Programming the Cell Scheduling System 38 Guaranteeing the availability of a location in the Connection ID table 41 The PUSHC/POPC instruction buffer 42 POPC, PUSHC, POPF, and PUSHF instruction operation POPC and PUSHC timing 42 POPF and PUSHF timing 42 Connection ID table and Scoreboard addressing 43 42 Initializing the Scoreboard 45 Selecting a Scoreboard size 45 Supporting multiple Scoreboard sections 46 CHAPTER 4 The Fast Memory Interface Loading 48 Storing 50 47 48 SWAN processor accesses to Fast Memory Cell Scheduling System accesses to Fast Memory 51 SWAN executable fetches from Fast Memory 51 Fast Memory configurations 52 Memory sizes supported 52 RAM selection and configuration 53 iv MXT3010 Reference Manual Mode 0 operation 53 Mode 1 operation 54 Bus contention avoidance 55 Fast Memory sequence diagrams 56 CHAPTER 5 The Cell Buffer RAM 59 Internal cell storage in the Cell Buffer RAM 60 Cell Buffer RAM memory construction 64 Cell Buffer RAM access 67 CHAPTER 6 The UTOPIA port.
Key Features
- 4 MXT3010 subsystems 5 What information is in this manual
