MT90500 Overview
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. Mapping between CBR-AAL0, CBR-AAL5, and AAL1 Mapping between CBR partially-filled cells and full cells Mapping between CBR single-voice cells and Nx64 cells.
MT90500 Key Features
- AAL1 Segmentation and Reassembly device patible with Structured Data Transfer (SDT) as per ANSI T1.630 and ITU I.363 sta
- Transports 64kbps and N x 64kbps traffic over ATM AAL1 cells (also over AAL5 or AAL0)
- Simultaneous processing of up to 1024 bidirectional Virtual Circuits
- Flexible aggregation capabilities (Nx64) to allow any bination of 64 kbps channels while maintaining frame integrity (DS
- Support for clock recovery
- Adaptive Clock Recovery, Synchronous Residual Time Stamp (SRTS), or external
- Primary UTOPIA port (Level 1, 25 MHz) for connection to external PHY devices with data throughput of up to 155 Mbps
- Secondary UTOPIA port for connection to an external AAL5 SAR processor, or for chaining multiple MT90500 devices
- 40°C to +85°C
- 16-bit microprocessor port, configurable to Motorola or Intel timing