PDSP16116BB0AC Datasheet | Mitel Networks Corporation

PDSP16116 16 X 16 Bit plex Multiplier Supersedes October 1996 version, DS3707 - 4.2 DS3707 - 5.3 October 1997 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two plex (16116) bit words every 50ns and can be configured to output the plete plex (32132) bit result within a single cycle. The data format is fractional two’s plement. In bination with a PDSP16318A, the PDSP16116A forms a two-chip 20MHz plex multiplier accumulator with 20-bit accumulator registers and output shifters. The PDSP16116A...