SP5848 Datasheet | Mitel Networks

Preliminary Information 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL Preliminary Information DS5076 Issue 1.6 October 1999 Features Ordering Information SP5848/KG/QP1S SP5848/KG/QP1T Dual independent PLL frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application 2.2GHz up-synthesiser optimised for low phase noise up to parison frequencies of 4MHz 1.3GHz down-synthesiser optimised for low phase noise AND small step size mon reference oscillator and divider with independently selectable ratios for each synthesiser 10:1 programmable charge pump current ratio in up synthesiser 3-Wire bus programmable, each synthesiser indepently addressable Low power consumption, typ 100m W at 5V ESD protection, (Normal ESD handling procedures should be observed) Description The SP5848 is a dual PLL frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners. Each synthesiser loop within the SP5848 is independently addressable and contains an RF programmable divider, phase/frequency detector and charge pump/loop amplifier section; a mon reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable. Both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low parison frequency. Applications TV, VCR, and cable tuning systems PUMP 1 11 BIT COUNT RF1 INPUT 16/17 4 BIT COUNT DRIVE 1 15 BIT LATCH 2 BIT LATCH DATA CLOCK ENABLE DATA INTERFACE 5 BIT LATCH 29 DIVIDE 2 BIT LATCH PORT P0 PORT P1 16 BIT LATCH 1 BIT LATCH PUMP 2 12 BIT COUNT RF 2 INPUT 16/17 4 BIT COUNT DRIVE 2 Figure 1 Block Diagram Preliminary Information PORT P1 CHARGE PUMP 2 DRIVE 2 Vee 2 RF2 INPUT RF2 INPUT Vcc2 CRYSTAL CRYSTAL CAP Vee PORT P0 CHARGE PUMP 1 DRIVE 1 Vee 1 RF1 INPUT RF1 INPUT Vcc1 ENABLE DATA CLOCK QP20 Figure...