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S40B - 64M bit Synchronous DRAM

Description

M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface.

All inputs and outputs are referenced to the rising edge of CLK.

Features

  • ITEM tCLK tRAS tRCD tAC tRC Icc1 Icc6 Clock Cycle Time (Min. ) (Min. ) (Min. ) (Max. ) (CL=3) (Min. ) M2V64S20TP M2V64S30TP M2V64S40TP -6 7.5ns 45ns 20.0ns 5.4ns 67.5ns 120mA (Max. ) 1mA Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max. ) [Single Bank] Self Refresh Current - Single 3.3V ±0.3V power supply - Max. Clock frequency -6 : 133MHz [PC133 ] - Fully synchronous operation referenced to clock rising edge - 4-bank.

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Datasheet Details

Part number S40B
Manufacturer Mitsubishi Electric Semiconductor
File Size 655.47 KB
Description 64M bit Synchronous DRAM
Datasheet download datasheet S40B Datasheet
Additional preview pages of the S40B datasheet.

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    Full PDF Text Transcription

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    PC133 SDRAM (Rev.0.5) Oct. '99 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT) MITSUBISHI LSIs PRELIMINARY Some of contents are described for general products and are subject to change without notice. DESCRIPTION M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.
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