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M2S28D40ATP - 128M Double Data Rate Synchronous DRAM

Download the M2S28D40ATP datasheet PDF. This datasheet also covers the M2S variant, as both devices belong to the same 128m double data rate synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Key Features

  • - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmabl.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M2S-28D.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Mitsubishi Electric

Part Number Description
M2S28D40ATP-10 128M Double Data Rate Synchronous DRAM
M2S28D40ATP-75 128M Double Data Rate Synchronous DRAM
M2S28D20ATP 128M Double Data Rate Synchronous DRAM
M2S28D20ATP-10 128M Double Data Rate Synchronous DRAM
M2S28D20ATP-75 128M Double Data Rate Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems. FEATURES - Vdd=Vddq=2.5V+0.