M2S56D20ATP - 256M Double Data Rate Synchronous DRAM

Product Overview

Mitsubishi

Datasheet Details

Part number	M2S56D20ATP
Manufacturer	Mitsubishi
File Size	815.69 KB
Description	256M Double Data Rate Synchronous DRAM
Datasheet	M2S56D20ATP Datasheet
Additional preview pages of the M2S56D20ATP datasheet.

Product details

Description

M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit, M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit, M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

Features

- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmabl.

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Published: Aug 29, 2015 |