M2S56D40AKT-75A Overview
All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieve very high speed data rate up to 133MHz, and are suitable for main memory in puter systems.
M2S56D40AKT-75A Key Features
- VDD=VDDQ=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
- mands are entered on each positive CLK edge
- Data and data mask are referenced to both edges of DQS
- 4-bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)