M2S56D40ATP-75AL - 256M Double Data Rate Synchronous DRAM

This page provides the datasheet information for the M2S56D40ATP-75AL, a member of the M2S 256M Double Data Rate Synchronous DRAM family.

Product Overview

Mitsubishi

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Datasheet Details

Part number	M2S56D40ATP-75AL
Manufacturer	Mitsubishi
File Size	768.53 KB
Description	256M Double Data Rate Synchronous DRAM
Datasheet	M2S56D40ATP-75AL Datasheet
Additional preview pages of the M2S56D40ATP-75AL datasheet.

M2S56D40ATP-75AL Product details

Description

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

Features

- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and data mask are referenced to both edges of DQS - 4-bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- seque.

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Other Datasheets by Mitsubishi

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Published: May 2, 2005 |