M5M54R01AJ-12 Datasheet | Mitsubishi Electric

MITSUBISHI LSIs 1998.11.30 Ver.B PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M54R01AJ-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M54R01AJ is a family of 4194304-word by 1-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL patible. They include a power down feature as well. address inputs chip select input A0 A1 A2 A3 A4 A5 S D W A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Features - Fast access time M5M54R01AJ-12 ... 12ns(max) M5M54R01AJ-15 ... 15ns(max) (3.3V) VCC (0V) GND data inputs write control input address inputs - Single +3.3V power supply - Fully static operation : No clocks, No refresh - Easy memory expansion by S - Three-state outputs : OR-tie capability - OE prevents data contention in the I/O bus - Directly TTL patible : All inputs and outputs A21 A20 address A19 inputs A18 A17 A16 output enable OE input GND (0V) VCC (3.3V) data outputs Q A15 A14 address A13 inputs A12 A11 control B1/B4 byte input Outline 32P0K APPLICATION High-speed memory units PACKAGE M5M54R01AJ : 32pin 400mil SOJ BLOCK DIAGRAM A0 A1 A2 A3 address...