M5M5T5636GP-25 Description
The M5M5T5636GP is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability.
M5M5T5636GP-25 Key Features
- Fully registered inputs and outputs for pipelined operation
- Fast clock speed: 250, 225 and 200 MHz
- Fast access time: 2.6, 2.8 and 3.2 ns
- Single 2.5V -5% and +5% power supply VDD
- Separate VDDQ for 2.5V or 1.8V I/O
- Individual byte write (BWa#
- BWd#) controls may be tied
- Single Read/Write control pin (W#)
- CKE# pin to enable clock and suspend operations
- Internally self-timed, registers outputs eliminate the need