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M5M5V5636GP16 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Datasheet Summary

Description

The M5M5V5636GP is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Features

  • Fully registered inputs and outputs for pipelined operation.
  • Fast clock speed: 167 MHz.
  • Fast access time: 3.8 ns.
  • Single 3.3V -5% and +5% power supply VDD.
  • Separate VDDQ for 3.3V or 2.5V I/O.
  • Individual byte write (BWa# - BWd#) controls may be tied LOW.
  • Single Read/Write control pin (W#).
  • CKE# pin to enable clock and suspend operations.
  • Internally self-timed, registers outputs eliminate the need to control G#.

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Datasheet Details

Part number M5M5V5636GP16
Manufacturer Mitsubishi
File Size 262.21 KB
Description 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Datasheet download datasheet M5M5V5636GP16 Datasheet
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Full PDF Text Transcription

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2001.July Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5V5636GP –16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM DESCRIPTION The M5M5V5636GP is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V I/O supply or a single 3.3V power supply and are 3.3V CMOS compatible. APPLICATION High-end networking products that require high bandwidth, such as switches and routers.
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