M66256FP Description
The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput.
M66256FP Key Features
- Memory configuration
- 5120 words × 8-bits (dynamic memory)
- High-speed cycle
- 25ns (Min.)
- High-speed access
- 18ns (Max.)
- Output hold
- 3ns (Min.)
- Fully independent, asynchronous write and read operations
- Variable length delay bit