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M66850FP - SRAM TYPE FIFO MEMORY

Description

M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology.

These FIFOs are applicable for a data buffer as networks and communications.

Features

  • Memory configuration 64words x 9bits (M66850J/FP) 256words x 9bits (M66851J/FP) 512words x 9bits (M66852J/FP) 1024words x 9bits (M66853J/FP) Write and Read Clocks can be independent Advanced CMOS technology Programmable Almost-Empty and Almost-Full flags High-speed : 25ns cycle time Package Available : 32-pin Pastic Leaded Chip Carrier(PLCC) 32-pin Low profile Quad Flat Package(LQFP) D1 D0 PAF PAE GND 1 2 3 4 5.
  • REN1 6 RCLK 7 REN2 8 EF.

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Datasheet preview – M66850FP

Datasheet Details

Part number M66850FP
Manufacturer Mitsubishi
File Size 118.18 KB
Description SRAM TYPE FIFO MEMORY
Datasheet download datasheet M66850FP Datasheet
Additional preview pages of the M66850FP datasheet.

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Full PDF Text Transcription

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MITSUBISHI M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY PIN CONFIGURATION (TOP VIEW) 2 D4 1 D5 32 D6 31 D7 30 D8 29 RS 28 WEN1 27 WCLK 26 WEN2/LD 25 VCC 24 Q8 23 Q7 22 Q6 21 Q5 4 D2 3 D3 DESCRIPTION M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology. These FIFOs are applicable for a data buffer as networks and communications. The write operation is controlled by a write clock pin(WCLK) and two write enable pins(WEN1,WEN2). Data present at the data input pins(D0-D8) is written into the Synchronous FIFO on every rising write clock edge when the device is enabled for writing. The read operation is controlled by a read clock pin(RCLK) and two read enable pins(REN1,REN2).
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