P3S56D40ETP Overview
All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memory in puter systems.
P3S56D40ETP Key Features
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- mands entered on each positive CLK edge
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)