V53C316405A Datasheet PDF (3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM)

V53C316405A - 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM

Description

The V53C316405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory.

The V53C316405A offers Page mode operation with Extended Data Output.

The V53C316405A has asymmetric address, 12-bit row and 10-bit column.

Features

s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh and Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +3.3V ± 0.3V Power Supply s TTL Interface.

Datasheet Details

Part number	V53C316405A
Manufacturer	Mosel Vitelic Corp
File Size	171.12 KB
Description	3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM
Datasheet	V53C316405A Datasheet
Additional preview pages of the V53C316405A datasheet.

📁 Similar Datasheet

V53C104 - High Performance / Low Power 256k x 4 Bit / Fast Page Mode CMOS DRAM (Vitelic)

V53C104A - High Performance / Low Power 256k x 4 Bit / Fast Page Mode CMOS DRAM (Vitelic)

V53C104B - High Performance / Low Power 256k x 4 Bit / Fast Page Mode CMOS DRAM (Vitelic)

V53C104D - High Performance / Low Power 256k x 4 Bit / Fast Page Mode CMOS DRAM (Vitelic)

V53C104F - High Performance / Low Power 256k x 4 Bit / Fast Page Mode CMOS DRAM (Vitelic)

V53C104H - Ultra-High Performance / Low Power 256k x 4 Bit / Fast Page Mode CMOS DRAM (Vitelic)

V53C16258SH - HIGH PERFORMANCE 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM SELF REFRESH (Mosel Vitelic)

V53C1664H - High Performance Fast Page Mode Dual Cas CMOS Dynamic RAM (Mosel-Vitelic)

V53C256A - (V53C256A Series) High Performance / Low Power 256k x 1-Bit Fast Page Mode CMOS DRAM (Vitelic)

V53C256P80L - (V53C256A Series) High Performance / Low Power 256k x 1-Bit Fast Page Mode CMOS DRAM (Vitelic)

Full PDF Text Transcription

Click to expand full text

MOSEL VITELIC V53C316405A 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C316405A Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh and Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +3.3V ± 0.3V Power Supply s TTL Interface Description The V53C316405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory.

Published: Apr 16, 2005 |