V62C318256 Overview
The V62C318256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL patible and allow for direct interfacing with mon system bus structures.
V62C318256 Key Features
- TTL Standby: 0.5 mA (Max.)
- CMOS Standby: 10 µA (Max.) I Fully static operation I All inputs and outputs directly patible I Three state outputs I Ul
- 28-pin TSOP (Standard)
- 28-pin 300 mil SOP (450 mil pin-to-pin)
- Access Time (ns) 35
- Power LL
- Temperature Mark Blank I