Datasheet Summary
SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS109A consists of two high speed pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
SET (SD) 5(11) Q CLEAR (CD) 1(15) CLOCK 4(12) Q 7(9) J 2(14) 6(10)
J SUFFIX CERAMIC CASE 620-09
16 1
K 3(13)
16 1
N SUFFIX PLASTIC CASE 648-08
MODE SELECT
- TRUTH TABLE
INPUTS OPERATING MODE SD Set Reset (Clear)
- Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) L H...
