SN54LS109A Description
SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.
SN54LS109A Key Features
- K X X X h h
- l Q H L H H q q L Q L H H L q q H OUTPUTS 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74