SN54LS112A Overview
SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop.
SN54LS112A Key Features
- TRUTH TABLE
- Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH sim
- High Output Current
- 0.4 4.0 8.0 Unit V °C mA mA
- 20 0.35 0.5 20 60 80 0.1 0.3 0.4
- 100 6.0 V µA 2.5 2.7 54 74
- 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8
- 1.5 V V V V Typ Max Unit V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage f
- 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH p
