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SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address.
SN54LS256 Datasheet
