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SN54LS323 - 8-BIT SHIFT/STORAGE REGISTER

General Description

The logic diagram and truth table indicate the functional characteristics of the SN54/74LS323 Universal Shift/Storage Register.

This device is similar in operation to the SN54/74LS299 except for synchronous reset.

Key Features

  • are described below: 1. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control (S0, S1) and data inputs (DS0, DS7, I/O0.
  • I/O7) may be stable at least a setup time prior to the positive transition of the Clock Pulse. 2. When S0 = S1 = 1, I/O0.
  • I/O7 are parallel inputs to flip-flops Q0.
  • Q7 respectively, and the outputs of Q0.
  • Q7 are in the high im.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
SN54LS32 QUAD 2-INPUT OR GATE
SN54LS322A 8-BIT SHIFT REGISTERS
SN54LS30 8-INPUT NAND GATE
SN54LS33 QUAD 2-INPUT NOR BUFFER
SN54LS348 8-INPUT PRIORITY ENCODERS
SN54LS352 DUAL 4-INPUT MULTIPLEXER
SN54LS353 DUAL 4-INPUT MULTIPLEXER
SN54LS365A 3-STATE HEX BUFFERS
SN54LS37 QUAD 2-INPUT NAND BUFFER
SN54LS373 OCTAL TRANSPARENT LATCH

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS323 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Its function is similar to the SN54 / 74LS299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right, and parallel load. All modes are activated on the LOW-to-HIGH transition of the Clock.