Description
Part II
Reset and Configuration Reset, Clocking, and Initialization System Configuration Part III
Core and I/O Interfaces Arbiter and Bus Monitor e300 Processor Core Overview Integrated Programmable Interrupt Controller (IPIC) DDR Memory Controller Local Bus Controller Sequencer DMA
Features
- of the QUICC Engine Block Compared with the CPM 1-13 Software Migration from the MPC82xx/MPC85xx Family Devices 1-14 Serial Protocol Table 1-15 QUICC Engine Configurations 1-16 Security Engine 1-16 Dual DDR Memory Controllers 1-17 PCI Controller 1-18 PCI Bus Arbitration Unit 1-18 Local Bus Controller (LBC) 1-18 Integrated Programmable Interrupt Controller (IPIC) 1-19 Dual I2C Interfaces 1-20 DMA Controller 1-20 Dual Universal Asynchronous Receiver/Transmitter (DUART) 1-21 System Timers.
MPC8360E Datasheet
