54LS123 Overview
Key Features
- Overriding Clear Terminates Output Pulse
- Compensated for VCC and Temperature Variations
- DC Triggered from Active-High or Active-Low Gated Logic Inputs
- Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
- Internal Timing Resistors on LS122 SN54 / 74LS123 (TOP VIEW) (SEE NOTES 1 THRU
- An external timing capacitor may be connected between Cext and Rext/Cext (positive)
- To use the internal timing resistor of the LS122, connect Rint to VCC
- For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited
