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54LS75 - 4-BIT D LATCH

This page provides the datasheet information for the 54LS75, a member of the 54LS77 4-BIT D LATCH family.

Features

  • complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density.

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Datasheet preview – 54LS75

Datasheet Details

Part number 54LS75
Manufacturer Motorola
File Size 70.38 KB
Description 4-BIT D LATCH
Datasheet download datasheet 54LS75 Datasheet
Additional preview pages of the 54LS75 datasheet.

📁 Similar Datasheet

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Other Datasheets by Motorola
  • 54LS76A - DUAL JK FLIP-FLOP
  • 54LS77 - 4-BIT D LATCH
  • 54LS04 - HEX INVERTER
  • 54LS122 - RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
  • 54LS123 - RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
  • 54LS138 - 1-OF-8 DECODER/DEMULTIPLEXER
  • 54LS155 - DUAL 1-OF-4 DECODER/DEMULTIPLEXER
  • 54LS156 - DUAL 1-OF-4 DECODER/DEMULTIPLEXER

Full PDF Text Transcription

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4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. The SN54 / 74LS75 features complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted.
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