56F801 - 16-bit Hybrid Controller

Product Overview

Motorola

Datasheet Details

Part number	56F801
Manufacturer	Motorola
File Size	887.01 KB
Description	16-bit Hybrid Controller
Datasheet	56F801 Datasheet
Additional preview pages of the 56F801 datasheet.

Product details

Description

Eleven multiplexed General Purpose I/O (GPIO) pins Computer-Operating Properly (COP) watchdog timer One dedicated external interrupt pin External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller core clock Oscillator flexibility between either an external crystal osc

Features

1.1.1.
Digital Signal Processing Core Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel in.

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Published: Nov 9, 2006 |