74LS112A Datasheet Dual Jk Negative Edge-triggered Flip-flop

Manufacturer: Motorola Semiconductor (now NXP Semiconductors)

Overview: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	74LS112A
Manufacturer	Motorola Semiconductor (now NXP Semiconductors)
File Size	147.34 KB
Description	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Datasheet	74LS112A 74LS112 Datasheet (PDF)

Key Features

individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. SN54/74LS112A DUAL JK.

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Similar Datasheet

Brand Logo	Part Number	Description	Manufacturer
	74LS112A	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop	Fairchild Semiconductor
	74LS112	Dual J-K Negative-edge-triggered Flip-Flops	Hitachi Semiconductor

More Datasheets from Motorola Semiconductor (now NXP Semiconductors)

Part Number	Description
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