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74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Download the 74LS112A datasheet PDF. This datasheet also covers the 74LS112 variant, as both devices belong to the same dual jk negative edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. SN54/74LS112A DUAL JK.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LS112_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop Fairchild Semiconductor
74LS112 Dual J-K Negative-edge-triggered Flip-Flops Hitachi Semiconductor
74LS11 Triple 3-Input AND Gate Fairchild Semiconductor
74LS10 TRIPLE 3-INPUT NAND GATE ON Semiconductor
74LS10 Triple 3-Input NAND Gate Fairchild Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
74LS12 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
74LS122 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
74LS125 QUAD 3-STATE BUFFERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.