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74LS161 - BCD DECADE COUNTERS/4-BIT BINARY COUNTERS

Datasheet Summary

Description

The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature.

The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs.

Features

  • th th trec.
  • CEP, CET or DATA Parameter Clock Pulse Width Low MR or SR Pulse Width Setup Time, other.
  • Setup Time PE or SR Hold Time, data Hold Time, other Recovery Time MR to CP Min 25 20 20 25 3 0 15 Typ Max Unit ns ns ns ns ns ns ns Test Conditions VCC = 5.0 V.

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Datasheet preview – 74LS161

Datasheet Details

Part number 74LS161
Manufacturer Motorola
File Size 157.94 KB
Description BCD DECADE COUNTERS/4-BIT BINARY COUNTERS
Datasheet download datasheet 74LS161 Datasheet
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Full PDF Text Transcription

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BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (binary.) The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge.
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