Motorola DSP56366
The DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56366 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony™ DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescale’s popular 56000 Symphony family of DSPs while retaining code compatibility.| Part No. | DSP56366 |
|---|---|
| Datasheet | DSP56366 Download |
| Manufacturer |  Motorola |
| Description | Digital Signal Processor |
| Buy | Stock & Price |
FEATURES
DSP56300 Modular Chassis 120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V. Object Code Compatible with the 56K core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support and instruction cache support. Six-channel DMA controller. PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise. Internal address tracing support and OnCE™ for Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down to DC. STOP and WAIT low-power standby modes. 1.1.2●
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● On-chip Memory Configuration 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM. 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM. 40Kx24 Bit Program ROM. 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as Instruction Cache or for Program ROM patching.
