Description
Sixteen (16) dedicated general purpose I/O (GPIO) pins Thirty (30) shared general purpose I/O (GPIO) pins Computer-Operating Properly (COP) Watchdog timer Two external interrupt pins External reset pin for ha
Features
- 1.1.1.
- Digital Signal Processing Core
Efficient 16-bit DSP56800 Family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction.
DSP56F826 Datasheet
