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MC100E016 - 8-Bit Synchronous Binary Up Counter

Key Features

  • internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly.

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📁 Similar Datasheet

Part Number Description Manufacturer
MC100E016 8-BIT SYNCHRONOUS BINARY UP COUNTER ON Semiconductor
MC100E101 QUAD 4-INPUT OR/NOR GATE ON Semiconductor
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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MC100E101 Quad 4-Input OR/NOR Gate
MC100E104 QUINT 2-INPUT AND/NAND GATE
MC100E107 QUINT 2-INPUT XOR/XNOR GATE
MC100E111 1:9 DIFFERENTIAL CLOCK DRIVER
MC100E112 QUAD DRIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8ĆBit Synchronous Binary Up Counter MC10E016 MC100E016 The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter.